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Ultra-Low Voltage VDCC Design by Using DTMOS

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dc.contributor.authorBasak, M. E.
dc.contributor.authorKacar, F.
dc.date.accessioned2026-06-27T13:54:47Z
dc.date.issued2016
dc.description.abstractIn this paper, a new ultralow voltage and ultralow power voltage differencing current conveyor based on dynamic threshold voltage MOS transistors was proposed. The simulations were performed by using LTSpice Program with TSMC CMOS 0.18 mu m process parameters. A new notch filter configuration was also presented as an application for the proposed voltage differencing current conveyor. The power consumption of proposed voltage differencing current conveyor was simply 12.42 nW at symmetric +/- 0.2 V supply voltage. The simulation results were found in close agreement with the theoretical results.en
dc.description.urihttps://doi.org/10.12693/aphyspola.130.223
dc.identifier.doi10.12693/aphyspola.130.223
dc.identifier.eissn1898-794X
dc.identifier.endpage225
dc.identifier.issn0587-4246
dc.identifier.issue1
dc.identifier.startpage223
dc.identifier.urihttps://hdl.handle.net/20.500.14981/55618
dc.identifier.volume130
dc.identifier.wos000384810700058
dc.language.isoeng
dc.publisherPOLISH ACAD SCIENCES INST PHYSICS
dc.relation.conference2nd International Conference on Computational and Experimental Science and Engineering (ICCESEN)
dc.relation.ispartofACTA PHYSICA POLONICA A
dc.rightsopenAccess
dc.subjectCIRCUITS
dc.subjectPhysics
dc.titleUltra-Low Voltage VDCC Design by Using DTMOS
dc.typeArticle; Proceedings Paper
dspace.entity.typePublication
local.import.sourceWOS

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