A single-phase solid-state fault current limiter: Simulation and experimental study

Abstract

Various methods are used to reduce fault currents in fault situations occurring in power systems. In this study, a developed single-phase power electronics -based solid-state fault current limiter is presented. The proposed single-phase solid-state fault current limiter is designed as preliminary prototype of the three-phase low voltage solid-state fault current limiter. The maximum current and voltage capability of the fault current limiter is 16 A and 480 V. This limiter works according to the principle of series and parallel resonance. In normal operation, the current passes through the inductance and capacitor, which are in series resonance. Thus, extra voltage drops and power loss in the system are prevented. In the event of a fault, the limiter switches to parallel resonance, and its impedance increases. Therefore, the fault current is decreased. The developed circuit and control algorithm reduces the first peak of fault current with a rather high percentage by comparison with the fault current without fault current limiter. In addition, the amplitude of current oscillation is decreased, and the current is recovered in a short time because the control algorithm determines the fault start and end time fast. The effect of the limiter is demonstrated with the simulation results in Matlab/Simulink. The simulation results are verified with the application study carried out in the laboratory environment. The fault current reaches up to 58.5 A in case of fault current limiter is not used, whereas the developed fault current limiter suppresses the current to around 9 A. The value of maximum fault current decreases to 15% according to the non -fault current limiter used situation. In the study, detailed application notes of the limiter circuit are shared.