A four-quadrant analog multiplier using DTMOS for low power applications

Abstract

The four-quadrant analog multipliers (FQAM) are widely used in signal processing applications such as amplitude modulation, frequency doubling, and adaptive filters. In this paper, a FQAM has been realised in dynamic threshold voltage MOSFET (DTMOS) technology. It relies on the square-law characteristics of the MOS transistor. Several simulations have been carried out to assess the operation of the proposed FQAM. The supply voltage is set to +/- 0.2 V, and 68 mu W power consumption is determined. The input signal can be applied to the full scale of the supply voltage. The bandwidth is 22.86 MHz, and the output signal's total harmonic distortion (THD) is less than 2%. Intermodulation products of the output signal have been calculated. Monte Carlo and temperature simulations have been performed in a way that confirms the robustness of the circuit against the technological spread. In summary, low power consumption, wide bandwidth, and linearity are the advantages of the proposed circuit.