Modeling and simulation of a General Regression Neural Network using Hardware Description Language

Abstract

This study presents the development of a synthesizable VHDL (Very High Speed Integrated Circuit Hardware Description Language) model of a General Regression Neural Network (GRNN). The GRNN has a four-layer structure which is comprised of an input layer, a pattern layer, a summation layer and an output layer. The designed system can be used for pattern classification applications. Iris dataset is used to test the GRNN in this study. Simulation results show that pattern classification by digital implementation of GRNN has successfully achieved.