Technology Development and Modeling of Switching Lattices Using Square and H Shaped Four-Terminal Switches

Abstract

Switching lattices formed by four-terminal switches are introduced as dense rectangular structures to implement Boolean logic functions. It is clearly shown in literature by a variety of logic synthesis algorithms including the exact one, realizing logic functions on lattices with the fewest number of four-terminal switches, as well as the heuristic ones, that switching lattices offer a significant area advantage in terms of the number of switches over the conventional CMOS implementations. Although the computing potential of switching lattices has been well justified, the same thing cannot be said for their physical implementation. There have been conceptual ideas for the technology development of switching lattices, but no concrete and directly applicable technology has been proposed yet. In this study, we show that switching lattices can be implemented using the CMOS technology. For this purpose, we propose two different four-terminal switch structures with square and H shaped gates. We construct these two structures in three dimensional technology computer-aided design (TCAD) environment satisfying the design rules of the TSMC 65 nm CMOS process and perform simulations. Then, we develop Level 3 DC and AC models of these four-terminal switches in LTspice environment using the TCAD simulation data. As an experiment, we realize logic functions with the developed models using static and dynamic logic solutions. Experimental results show that the realization of logic functions using switching lattices occupy much less layout area and have competitive delay and power consumption values when compared to the conventional CMOS implementations.