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An FPGA implementation of 2-D CNN Gabor-type filter

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dc.contributor.authorSaatci, Ertugrul
dc.contributor.authorCesur, Evren
dc.contributor.authorTavsanoglu, Vedat
dc.contributor.authorKale, Izzet
dc.date.accessioned2026-06-27T13:05:10Z
dc.date.issued2007
dc.description.abstractA field programmable gate array (FPGA) implementation of the Gabor-type filter is presented. The implementation uses the forward Euler approximation with optimal step size to solve the CNN cell-state equation. The FPGA is implemented on Xilinx Spartan XC3S400 device using 219 slices. An image of dimension 60 x 60 can be processed without using any external RAM only with the block RAM.en
dc.description.sponsorshipYildiz Technical University Scientific Research Projects Coordination Department [25-04-03-01]
dc.description.urihttps://doi.org/10.1109/ecctd.2007.4529591
dc.identifier.doi10.1109/ecctd.2007.4529591
dc.identifier.endpage+
dc.identifier.isbn978-1-4244-1341-6
dc.identifier.startpage280
dc.identifier.urihttps://hdl.handle.net/20.500.14981/49506
dc.identifier.wos000258708400071
dc.language.isoeng
dc.publisherIEEE
dc.relation.conference18th European Conference on Circuit Theory Design
dc.relation.ispartof2007 EUROPEAN CONFERENCE ON CIRCUIT THEORY AND DESIGN, VOLS 1-3
dc.subjectEngineering
dc.titleAn FPGA implementation of 2-D CNN Gabor-type filter
dc.typeProceedings Paper
dspace.entity.typePublication
local.import.sourceWOS

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