Low Noise High Linearity Current Readout Topologies for Potentiostat Circuitry

Abstract

In this work, two current readout architectures are investigated for potentiostat design; bidirectional current conveyor based potentiostat (BCC-P) and first generation current conveyor based potentiostat (CCI-P). They are designed in CMOS 180 nm TSMC technology with standard 1.8 V supply voltage and are evaluated in terms of input referred noise, linearity, accuracy, current range and power consumption. The integrated input referred noise of the BCC-P and CCI-P circuits are 0.432 pA and 153 pA between 0.01 Hz - 1 kHz, respectively. Although each circuit has similar opamps circuits, BCC-P is found to be more advantageous in terms of current linearity and noise.