Adaptive piecewise linear characteristic approach for memristive synaptic circuits and FPGA implementation

Abstract

Artificial intelligence-based systems and synaptic circuits have become a topic of considerable interest for researchers in recent years. Since software implementation of these high computational power systems has become challenging in terms of time and processing costs, hardware implementation has emerged as a necessity. Hardware synaptic circuits promise to increase processing capacity while reducing power consumption and costs. The memristor element is a frequently used passive circuit component, and synaptic circuits implemented with memristors are termed memristive synaptic circuits. This study proposes a hardware method for memristive synaptic circuits. The proposed method aims to enable network structure reconfiguration by adjusting the memristance value of memristor elements, which correspond to artificial neural network weight parameters. A hardware design has been implemented to adjust memristor values, and an algorithm has been proposed to perform necessary operations. The design consists of sub-blocks that measure memristance values by applying sinusoidal signals and change memristance values by applying pulse signals. The proposed method has been implemented on FPGA and tested on mathematical memristor models. Results demonstrate that the method reduces required readwrite cycle counts, contributes to low power consumption, and provides an effective solution to the memristor nonlinearity problem.