Technology Independent Automated Sizing Methodology Based On Artificial Neural Networks: An Application to CMOS OPAMP Design

Abstract

This study introduces technology independent sizing for CMOS integrated opamp based on neural networks (NN). The aim is to predict the transistor sizes of integrated opamp that correspond to design constraints, without knowing the SPICE technology parameters. Furthermore, in contrast to other modeling researches, the output specifications of integrated circuits (IC) are predicted for new technology designs. First the design constraints were determined and several simulations were obtained using different sized transistors using Cadence Spectre Analog Environment. This means that the integrated opamp is designed for different transistor sizes (W, L) and different technologies those decreasing channel lengths. Eventually, a large database is developed for neural network. The novel thing is that the neural network was trained with the database including the simulation results of 1.5 mu m, 0.5 mu m, 0.35 mu m and 0.25 mu m technologies and the test data is constituted with only the simulation results of 0.18 mu m technology which were not applied to the neural network for training beforehand. The neural network gives the sizes of all transistors when a designer chooses the circuit topology and the technology and gives circuit output specifications. The designer should just choose opamp architecture and give the design output constraints to neural network. The neural network accepts circuit outputs as inputs and gives the transistors sizes as outputs.