Yayın:
An Automatic Formal Model Generation and Verification Method for Railway Interlocking Systems

dc.contributor.authorOz, Muhammed Ali
dc.contributor.authorKaymakci, Ozgur Turay
dc.date.accessioned2026-06-27T14:05:49Z
dc.date.issued2017
dc.description.abstractRailway transportation systems incorporate many safety critical systems such as signalization systems. Any possible failure within the scope of these safety critical systems can seriously harm the environment and lead to many life losses. Therefore design, development and the implementation of these sector specific products have been raised to a certain quality with the guidance of sector specific standards like EN 50126. Electronic interlocking system is one of the most important and essential product in railway transportation systems such that it controls railway traffic operation securely and prevents trains from colliding and also derailing. In this context, the developed algorithm must be automatically verified in order to ensure that the system will work totally reliable. In this paper, a new methodology using timed arc Petri nets is introduced in order to formally validate and verify railway interlocking system's correctness and safety. Also in order to reduce the human effort and possible implementation errors, a new software is developed using the programming language C#. The developed program automatically generates the formal models of the interlocking system through a visual interface. Here the safety requirements, which are written in CTL formulation, are verified on TAPAAL. Finally the obtained algorithm and models are implemented on an operational railway station by developed software in order to show the introduced method's effectiveness, accuracy and swiftness.en
dc.identifier.endpage147
dc.identifier.issn2147-1762
dc.identifier.issue2
dc.identifier.startpage133
dc.identifier.urihttps://hdl.handle.net/20.500.14981/56949
dc.identifier.volume30
dc.identifier.wos000405869900010
dc.language.isoeng
dc.publisherGAZI UNIV
dc.relation.ispartofGAZI UNIVERSITY JOURNAL OF SCIENCE
dc.subjectFormal verification
dc.subjectInterlocking
dc.subjectTimed arc Petri nets
dc.subjectRailway signalization systems
dc.subjectScience & Technology - Other Topics
dc.titleAn Automatic Formal Model Generation and Verification Method for Railway Interlocking Systems
dc.typeArticle
dspace.entity.typePublication
local.import.sourceWOS

Dosyalar

Koleksiyonlar