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Architecture of a Fully Pipelined Real-Time Cellular Neural Network Emulator

dc.contributor.authorYildiz, Nerhun
dc.contributor.authorCesur, Evren
dc.contributor.authorKayaer, Kamer
dc.contributor.authorTavsanoglu, Vedat
dc.contributor.authorAlpay, Murathan
dc.date.accessioned2026-06-27T13:38:29Z
dc.date.issued2015
dc.description.abstractIn this paper, architecture of a Real-Time Cellular Neural Network (CNN) Processor (RTCNNP-v2) is given and the implementation results are discussed. The proposed architecture has a fully pipelined structure, capable of processing full-HD 1080p@60 (1920 1080 resolution at 60 Hz frame rate, 124.4 MHz visible pixel rate) video streams, which is implemented on both high-end and low-cost FPGA devices, Altera Stratix IV GX 230, and Cyclone III C 25, respectively. Many features of the architecture are designed to be either pre-synthesis configurable or runtime programmable, which makes the processor extremely flexible, reusable, scalable, and practical.en
dc.description.sponsorshipScientific and Technological Research Council of Turkey (TUBITAK) [108E023]
dc.description.urihttps://doi.org/10.1109/tcsi.2014.2345502
dc.identifier.doi10.1109/tcsi.2014.2345502
dc.identifier.eissn1558-0806
dc.identifier.endpage138
dc.identifier.issn1549-8328
dc.identifier.issue1
dc.identifier.startpage130
dc.identifier.urihttps://hdl.handle.net/20.500.14981/54065
dc.identifier.volume62
dc.identifier.wos000347706500014
dc.language.isoeng
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
dc.relation.ispartofIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
dc.rightsopenAccess
dc.subjectCellular neural networks
dc.subjectfield programmable gate arrays
dc.subjectreal time systems
dc.subjectreconfigurable architectures
dc.subjectEngineering
dc.titleArchitecture of a Fully Pipelined Real-Time Cellular Neural Network Emulator
dc.typeArticle
dspace.entity.typePublication
local.import.sourceWOS

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