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On an Improved FPGA Implementation of CNN-Based Gabor-Type Filters

dc.contributor.authorCesur, Evren
dc.contributor.authorYildiz, Nerhun
dc.contributor.authorTavsanoglu, Vedat
dc.date.accessioned2026-06-27T13:15:49Z
dc.date.issued2012
dc.description.abstractIn this brief, the details of the architecture of a previously introduced improved field-programmable gate array implementation of the cellular neural network (CNN)-based 2-D Gabor-type filter are given, and the implementation results are discussed. The proposed architecture is suitable for real-time applications with high pixel rates. The prototype is capable of processing video streams up to a pixel rate of 373.2 megapixels per second (MP/s), including full-high-definition (HD) 1080p@60 (1080 x 1920 resolution, 60-Hz frame rate, and 124.4-MP/s visible pixel rate). This brief also contains convergence rate analysis results, along with some discussions on FIR and CNN-based implementation methods.en
dc.description.sponsorshipScientific and Technological Research Council of Turkey (TUBITAK) [108E023]
dc.description.urihttps://doi.org/10.1109/tcsii.2012.2218471
dc.identifier.doi10.1109/tcsii.2012.2218471
dc.identifier.eissn1558-3791
dc.identifier.endpage819
dc.identifier.issn1549-7747
dc.identifier.issue11
dc.identifier.startpage815
dc.identifier.urihttps://hdl.handle.net/20.500.14981/51193
dc.identifier.volume59
dc.identifier.wos000313426100024
dc.language.isoeng
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
dc.relation.ispartofIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS
dc.subjectCellular neural networks (CNNs)
dc.subjectfield-programmable gate arrays (FPGAs)
dc.subjectGabor filters
dc.subjectreal-time systems
dc.subjectreconfigurable architectures
dc.subjectEngineering
dc.titleOn an Improved FPGA Implementation of CNN-Based Gabor-Type Filters
dc.typeArticle
dspace.entity.typePublication
local.import.sourceWOS

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