Metaheuristics Based CMOS Two-Stage Comparator Optimization

Abstract

This paper investigates nature-inspired metaheuristics for optimized sizing of a CMOS comparator with PMOS input driver. The aim is to minimize MOS transistor area using two nature-inspired metaheuristics, differential evolution and harmony search. Simulation results demonstrate that design specifications are closely met and required functionalities are accommodated in short computational time while area optimization criterion is satisfied.