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Metaheuristics Based CMOS Two-Stage Comparator Optimization

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dc.contributor.authorVural, Reyna Acar
dc.contributor.authorBozkurt, Ufuk
dc.contributor.authorYildirim, Tulay
dc.contributor.institutionauthorYILDIRIM, Tülay
dc.date.accessioned2026-06-27T13:27:51Z
dc.date.issued2013
dc.description.abstractThis paper investigates nature-inspired metaheuristics for optimized sizing of a CMOS comparator with PMOS input driver. The aim is to minimize MOS transistor area using two nature-inspired metaheuristics, differential evolution and harmony search. Simulation results demonstrate that design specifications are closely met and required functionalities are accommodated in short computational time while area optimization criterion is satisfied.en
dc.identifier.endpage650
dc.identifier.isbn978-988-19253-1-2
dc.identifier.issn2078-0958
dc.identifier.startpage645
dc.identifier.urihttps://hdl.handle.net/20.500.14981/52868
dc.identifier.volumeAo,
dc.identifier.wos000335870300011
dc.language.isoeng
dc.publisherINT ASSOC ENGINEERS-IAENG
dc.relation.conferenceWorld Congress on Engineering and Computer Science
dc.relation.ispartofWORLD CONGRESS ON ENGINEERING AND COMPUTER SCIENCE, WCECS 2013, VOL II
dc.subjectconstrained optimization
dc.subjectanalog integrated circuits
dc.subjectautomated design
dc.subjecttransistor sizing
dc.subjectmetaheuristics
dc.subjectANALOG
dc.subjectDESIGN
dc.subjectComputer Science
dc.subjectEngineering
dc.titleMetaheuristics Based CMOS Two-Stage Comparator Optimization
dc.typeProceedings Paper
dspace.entity.typePublication
local.import.sourceWOS

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