PATTERN RECOGNITION USING N-INPUT NEURON CIRCUITS BASED ON FLOATING GATE MOS TRANSISTORS

Abstract

In this paper, a neural network hardware implementation of pattern recognition using n-input neuron circuits is presented. Floating-gate MOS (FGMOS) based neuron model using four-quadrant analog multiplier with rail-to-rail linear input and FGMOS based differential comparator has been designed and simulated in HSPICE environment. Using the proposed low voltage neuron circuits a neural network was realized. Iris plant data set, which is one of the most well-known pattern recognition databases, was applied to test accuracy of the network.