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PATTERN RECOGNITION USING N-INPUT NEURON CIRCUITS BASED ON FLOATING GATE MOS TRANSISTORS

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dc.contributor.authorKeles, Fatih
dc.contributor.authorYildirim, Tuelay
dc.contributor.institutionauthorYILDIRIM, Tülay
dc.date.accessioned2026-06-27T13:06:33Z
dc.date.issued2009
dc.description.abstractIn this paper, a neural network hardware implementation of pattern recognition using n-input neuron circuits is presented. Floating-gate MOS (FGMOS) based neuron model using four-quadrant analog multiplier with rail-to-rail linear input and FGMOS based differential comparator has been designed and simulated in HSPICE environment. Using the proposed low voltage neuron circuits a neural network was realized. Iris plant data set, which is one of the most well-known pattern recognition databases, was applied to test accuracy of the network.en
dc.description.sponsorshipYIDZ Technical University Scientific Research Projects Coordination Department. [28-04-03-01]
dc.description.urihttps://doi.org/10.1109/eurcon.2009.5167634
dc.identifier.doi10.1109/eurcon.2009.5167634
dc.identifier.endpage+
dc.identifier.isbn978-1-4244-3967-6
dc.identifier.startpage224
dc.identifier.urihttps://hdl.handle.net/20.500.14981/49838
dc.identifier.wos000272589500039
dc.language.isoeng
dc.publisherIEEE
dc.relation.conferenceInternational IEEE Conference Devoted to the 150-Anniversary of Alexander S Popov
dc.relation.ispartofEUROCON 2009: INTERNATIONAL IEEE CONFERENCE DEVOTED TO THE 150 ANNIVERSARY OF ALEXANDER S. POPOV, VOLS 1- 4, PROCEEDINGS
dc.subjectNeuron circuits
dc.subjectFGMOS transistors
dc.subjectpattern recognition
dc.subjectclassification
dc.subjectneural network
dc.subjecthardware implementations
dc.subjectEngineering
dc.subjectPhysics
dc.titlePATTERN RECOGNITION USING N-INPUT NEURON CIRCUITS BASED ON FLOATING GATE MOS TRANSISTORS
dc.typeProceedings Paper
dspace.entity.typePublication
local.import.sourceWOS

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