LOW VOLTAGE LOW POWER NEURON CIRCUIT DESIGN BASED ON SUBTHRESHOLD FGMOS TRANSISTORS

Abstract

In this work, design of low-voltage low-power analog artificial neural network (ANN) circuit blocks by using subthreshold floating-gate MOS (FGMOS) transistors and a neuron circuit is implemented. The circuit blocks, four-quadrant analog current multiplier and FGMOS based differential pair, have been designed and simulated in CADENCE environment with TSMC 0.35. m process parameters.