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LOW VOLTAGE LOW POWER NEURON CIRCUIT DESIGN BASED ON SUBTHRESHOLD FGMOS TRANSISTORS

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dc.contributor.authorKeles, Fatih
dc.contributor.authorYildirim, Tulay
dc.contributor.institutionauthorYILDIRIM, Tülay
dc.date.accessioned2026-06-27T13:12:58Z
dc.date.issued2011
dc.description.abstractIn this work, design of low-voltage low-power analog artificial neural network (ANN) circuit blocks by using subthreshold floating-gate MOS (FGMOS) transistors and a neuron circuit is implemented. The circuit blocks, four-quadrant analog current multiplier and FGMOS based differential pair, have been designed and simulated in CADENCE environment with TSMC 0.35. m process parameters.en
dc.identifier.eissn1304-7191
dc.identifier.endpage177
dc.identifier.issn1304-7205
dc.identifier.issue2
dc.identifier.startpage170
dc.identifier.urihttps://hdl.handle.net/20.500.14981/50617
dc.identifier.volume29
dc.identifier.wos000219505400007
dc.language.isotur
dc.publisherYILDIZ TECHNICAL UNIV
dc.relation.ispartofSIGMA JOURNAL OF ENGINEERING AND NATURAL SCIENCES-SIGMA MUHENDISLIK VE FEN BILIMLERI DERGISI
dc.subjectNeuron circuits
dc.subjectsubthreshold
dc.subjectFGMOS transistors
dc.subjectlow voltage
dc.subjectlow power
dc.subjectneural network
dc.subjecthardware implementations
dc.subjectEngineering
dc.titleLOW VOLTAGE LOW POWER NEURON CIRCUIT DESIGN BASED ON SUBTHRESHOLD FGMOS TRANSISTORS
dc.typeArticle
dspace.entity.typePublication
local.import.sourceWOS

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